Natural Opinions

An Archive Of My Thoughts

  1. risc and cisc
    • Fixed length vs. variable length instructions
    • Operand use, number of operands and types (register-register also called load/store, register-memory, memory-memory)
    • addressing modes
    • microcoding vs. direct execution
  2. DLP (data level parallelism, SIMD/vector)
  3. ILP (instruction level parallelism, MIMD)
    • superscalar vs. vliw (and EPIC)
    • pipelining
      • pipeline length, instruction latency vs. clock frequency
    • out-of-order vs. in-order execution
      • instruction window size
      • pipeline width
      • control/reordering logic
  4. different bus designs (too many to list here)
  5. DMA engines vs. memory mapped I/O vs. port I/O
  6. von neumann vs. harvard and modified harvard architectures
  7. memory management models
    • segmented vs. continuous
    • linear vs. non-linear
    • physical vs. virtual
    • paging and page faults
  8. caching (way too many sub-topics to list)
  9. fetch logic and PC (program counter)
  10. decode logic, many different types
  11. ALU design
  12. when and when not to use multiplexing
  13. instructions
    • arithmetic
    • memory access
    • bitwise
    • logical
    • unconditional jump
    • conditional jump
    • comparison
  14. MMU design
  15. interrupt handling
  16. instruction set design
  17. TLP (thread level parallelism) and multiprocessing (way too much to list)
  18. DSPs
  19. GPUs
  20. microprocessors
  21. bit-slice processors
  22. microcontrollers
  23. and many, MANY more if you do some research

RISC cpus are typically:

  1. Fixed length instruction encoding/decoding
  2. Three operands for arithmetic/logical ops
  3. No memory operands except in load/store ops
  4. No or few microcoded instructions, direct execution instead
  5. Floating point done in software, no FPU (this was ignored by many designers though and quickly became unpopular)
  6. Big register set
  7. Big cache
  8. Tightly linked pipeline, no interlocks
  9. Bi-endian
  10. Use register windows (this was ignored by many designers though and quickly became unpopular)
  11. Use bypassing instead of interlocks to resolve data hazards (this became less popular over time)

Advantages:

  1. Very efficient pipeline allows for high IPC and high clock rates, which achieves high throughput
  2. Without memory operands in arithmetic/logical ops and without microcoded instructions pipeline stalls are far less frequent and shorter
  3. Three operand arithmetic/logical ops reduces number of mov needed
  4. A lot less transistors needed for decoding due to fixed length decoding and no microcode
  5. No FPU saves a lot of transistors too
  6. Big cache/register set reduces number of memory accesses needed
  7. Less transistors =  more energy/cost efficient if performance is not the goal
  8. Register windows reduce the number of load/store needed for context switching
  9. Bypassing allows the pipeline to resolve data hazards without inserting bubbles, which would reduce performance by increasing instruction latencies

Disadvantages:

  1. Because code is bigger more memory is needed which drives up system cost
  2. Because code is bigger memory accesses take longer, more memory and I/O bandwidth is needed
  3. Because code is bigger cache and register set need to be bigger to alleviate bandwidth problems
  4. No floating point unit obviously reduces floating point performance since it has to be done at the software level instead, which is slower
  5. Lack of microcoding means more instructions will be needed to complete the same task (most instructions in an application are usually simple instructions anyways so this isn't a big disadvantage)
  6. More dependance on compiler optimizations or assembly code programming to achieve good throughput
  7. Lack of complex instructions can make assembly programming and/or writing compilers more difficult, the need for lots of optimizations further compounds that
  8. Register windows reduces the number of registers available to programs to a level comparable to most cisc cpus
  9. Bypassing makes it difficult to increase the number of pipeline stages (to increase the clock rate) without significantly reducing the efficiency of the architecture